Multi-gate devices typically have two gates with a channel in between. One of the gates, the top gate, is above the channel, and the other gate, the bottom gate, is under the channel. The bottom gate is achieved without requiring much if any increase of the active area for a particular transistor. Among the benefits of multi-gate devices are increased current drive, a logic function for a single transistor when the bottom and top gates are independent, and elimination of drain induced barrier lowering. The applicability of multi-gate transistors has been adversely impacted by the difficulty in finding methods of making them that are manufacturable, that do not introduce additional issues, and that take advantage of the benefits of a multi-gate transistor.
Thus, there is a need for a technique that improves on the combination of desires to be manufacturable, not introduce additional issues, and take advantage of the benefits of a multi-gate transistor.